1 min readformal verificationhardwarenotes
What is formal verification?
A plain-language starting point for proofs, assertions, state spaces, and why bugs hide in hardware designs.
Overview
Formal verification is a way to prove that a design satisfies properties across many possible states, instead of only testing selected examples.
Why simulation is not enough
Simulation checks the examples you remembered to write. Formal methods ask whether a property can ever be broken across the reachable state space.
What I want to document next
The next useful step is collecting assertion patterns, counterexample stories, and small examples that connect proofs to real design intent.